1. Field of the Invention
The invention relates generally to analog-to-digital converters (ADCs), and more particularly to successive approximation register analog-to-digital converters (SAR ADCs).
2. Description of the Related Art
Successive approximation register analog to digital converters (SAR ADCs) transform an analog input signal into a digital output signal through a binary algorithm which performs binary bit-to-bit comparisons. In a typical SAR ADC, each bit of a digital code (representing a sample of the analog input signal) is determined in a single iteration, starting from the most significant bit. To determine the most significant bit, the most significant bit is set to a specific logical value (for example, 1) and the following bits to the other logical value (for example, 0), and the resulting number is converted to the intermediate analog signal (by using a digital to analog converter (DAC), contained in the ADC). The value of the most significant bit of the digital code is determined to equal 0 if the sample of the analog signal has less voltage than the intermediate analog signal; otherwise, the value of the most significant bit of the digital code is determined to be 1. The approach is continued until all the bits of the digital code are determined
For tolerating settling error, a type of SAR ADC uses redundant comparison cycles accomplished by using extra capacitors. However, in this type of SAR ADC, power consumption is increased because of increased input capacitance, and a signal-to-noise ratio worsens since an effective input range is lowered. Another type of SAR ADC uses double capacitor array DACs (digital to analog converters) to tolerate settling errors. Moreover, in this type of SAR ADC, more than one comparator is used. Accordingly, power consumption is increased and a larger area of the SAR ADC is required. Therefore, improving settling error tolerance without increasing power consumption or/and lowering efficiency is an important topic for SAR ADC development.